1. Field of the invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a precharge circuit.
2. Description of the Related Art
Recently, an improvement of memory device access speed is needed to increase microprocessor performance. However, as the memory capacity is increased, the number of memory cells connected to the pair of bit lines and the word lines is also increased, and the high speed operation becomes hard to be realized. For this reason, a memory device having an improved access time after precharging a pair of bit lines to a same potential is proposed.
Such as technique is disclosed in Japanese Patent Application Laid Open sho 59-178684. FIGS. 4(A) and 4(B) are a block diagram and a partial circuit diagram showing one column (first column of semiconductor memory cell array) of a semiconductor memory device having an address transition detector (ATD) system.
This semiconductor memory device comprises a plurality of memory cells MC1-MCn arranged in matrix form in row direction and column direction (only one column being indicated in FIG. 4(A)), a plurality of word lines WL1-WLn which bring the plurality of memory cells in a column to a selective state when they are at selection level, a plurality of mutually paired (only one pair being indicated in FIG. 4(A)) first bit line BL11 and second bit line BL12 provided corresponding to respective columns of the plurality of memory cells for transmitting write data and read data for memory cells in the selective state of the corresponding columns, load circuits 4 serving as loads to the memory cells in the selective state for supplying read data corresponding to stored data to the first and second bit line pairs and for transmitting and storing data transmitting from the bit line pairs to the memory cells, precharging circuits 1 which precharge the first and second bit line pairs to a power supply potential vdd in accordance with a precharging signal PC* (* indicates that the low level is the active level hereinafter), and a precharging signal generating circuit 21 which generates the precharging signal PC* by detecting changes in the address value of an address signal AD (with component bits A1-Am).
An address change detection circuit 21 as shown in FIG. 4(B) is provided for each of the component bit A1-Am of the address signal AD, in the precharging signal generating circuit 21 of this semiconductor memory device, and the precharging signal PC* is generated by integrating the outputs PC*i (`i` indicates a value from 1 to m) of these address change detection circuits 21.
In a semiconductor memory device, normally, precharging is started after all the word lines are brought to the non-selection level, and specified word lines are brought to the selection level, and specified word lines are brought to the selection level after complete release of the precharging, in order not to destroy data in the memory cell. Accordingly, in a semiconductor memory device which executes the precharging utilizing a precharging signal from the outside, the precharging signal is given a certain degree of margin of time from the setting of all the word lines to the non-selection level to the beginning of the precharging, and in the time from the release of the precharging to the selection of the word lines, by taking the operating times of the internal circuits into account.
For this reason, this prior art has a constitution in which the precharging is started by bringing the precharging signal PC* to the activation level after detecting changes of the component bits of the address signal AD to the low level, as shown in FIG. 5, so that the margin of time from the bringing of all the word lines to the non-selection level to the start of the precharging can be reduced, and the operating speed can be increased accordingly.
However, even in this semiconductor memory device, it is necessary, due to above-mentioned constitution of the device, to generate the precharging signal PC* so as to impart a certain degree of margin to all the memory cells as to the timing of the level change in the precharging signal PC* and the timings of the level change in the word lines t1 and t2. This fact imposes a difficulty on the further increase of the operating speed.
An example of a device which has a simple circuitry and yet enables to obtain an operating speed higher than that of the semiconductor memory device of ATD system, in which the precharging signal is generated after direct detection of level changes in the word lines, has been also proposed in this prior art.
Referring to FIG. 6, this semiconductor memory device receives the signal levels of a plurality of word lines WL1-WLn directly to a logic gate G11 of OR type and adopts its output as the precharging signal PC*. As shown in FIG. 7, high speed operation becomes possible, and yet circuity can be simplified drastically. However, there is absolutely no margin between the level change in the precharging signal PC* and the level change in the word lines.
In the above mentioned prior art semiconductor memory devices, the first example has a constitution in which the precharging signal PC* is generated by detecting the level change in the component bits A1-Am of the address signal AD. Therefore, the margin between the timing of the level change in the precharging signal PC* and the timing of the level change in the word line can be reduced compared with the case of a semiconductor memory device which is operated by receiving the precharging signal from the outside, and hence the operating speed can be increased accordingly. In spite of this, it is still necessary to give a certain degree of margin as to the two timings because the level changes in the word lines are not directly detected, and there remains a problem in that a further increase in the operating speed is difficult to realize.
On the other hand, the second example has a constitution in which the precharging signal PC* is generated by directly detecting the level change in the word lines so that there is absolutely no margin as to the two timings, enabling a further increase in the operating speed and a simplification of the circuit configuration. In spite of this, since, at the time of transition to the release of the precharging, the precharging signal PC* is brought to the deactivation level after detection of changes in the selection level of the word lines, the timing of connection of the memory cells to the bit lines owing to the selection level of the word lines overlaps with the timing of transition to the release of the precharging, which generates a possibility of destroying the stored contents of the memory cells.